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W83977EF-AW Datasheet(PDF) 64 Page - Winbond |
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W83977EF-AW Datasheet(HTML) 64 Page - Winbond |
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64 / 142 page  W83977EF-AW/W83977EG-AW -62- 7.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. 7.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011 When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned. When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system. 7.3.7 TFIFO (Test FIFO Mode) Mode = 110 Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines. 7.3.8 CNFGA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation. 7.3.9 CNFGB (Configuration Register B) Mode = 111 The bit definitions are as follows: 7 6 5 4 3 2 1 0 1 1 1 intrValue compress IRQx 0 IRQx 1 IRQx 2 Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. |
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