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W83977EF-AW Datasheet(PDF) 58 Page - Winbond |
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W83977EF-AW Datasheet(HTML) 58 Page - Winbond |
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58 / 142 page  W83977EF-AW/W83977EG-AW -56- 7.2.3 Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows: 1 1 1 2 3 4 5 6 70 STROBE AUTO FD SLCT IN IRQ ENABLE DIR INIT# Bit 7, 6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit is invalid and fixed at zero. Bit 4: A 1 in this position allows an interrupt to occur when ACK# changes from low to high. Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. 7.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows: 1 2 3 4 5 6 70 PD0 PD1 PD2 PD3 PD5 PD4 PD6 PD7 The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read cycle to be performed and the data to be output to the host CPU. |
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