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W83977EF-AW Datasheet(PDF) 47 Page - Winbond |
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W83977EF-AW Datasheet(HTML) 47 Page - Winbond |
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47 / 142 page  W83977EF-AW/W83977EG-AW Publication Release Date: Apr. 2006 -45- Revision 1.2 TABLE 6-1 UART Register Bit Map BIT NUMBER REGISTER ADDRESS BASE 0 1 2 3 4 5 6 7 + 0 BDLAB = 0 Receiver Buffer Register (Read Only) RBR RX Data Bit 0 RX Data Bit 1 RX Data Bit 2 RX Data Bit 3 RX Data Bit 4 RX Data Bit 5 RX Data Bit 6 RX Data Bit 7 + 0 BDLAB = 0 Transmitter Buffer Register (Write Only) TBR TX Data Bit 0 TX Data Bit 1 TX Data Bit 2 TX Data Bit 3 TX Data Bit 4 TX Data Bit 5 TX Data Bit 6 TX Data Bit 7 + 1 BDLAB = 0 Interrupt Control Register ICR RBR Data Ready Interrupt Enable (ERDRI) TBR Empty Interrupt Enable (ETBREI) USR Interrupt Enable (EUSRI) HSR Interrupt Enable (EHSRI) 0 0 0 0 + 2 Interrupt Status Register (Read Only) ISR "0" if Interrupt Pending Interrupt Status Bit (0) Interrupt Status Bit (1) Interrupt Status Bit (2)** 0 0 FIFOs Enabled ** FIFOs Enabled ** + 2 UART FIFO Control Register (Write Only) UFR FIFO Enable RCVR FIFO Reset XMIT FIFO Reset DMA Mode Select Reserved Reversed RX Interrupt Active Level (LSB) RX Interrupt Active Level (MSB) + 3 UART Control Register UCR Data Length Select Bit 0 (DLS0) Data Length Select Bit 1 (DLS1) Multiple Stop Bits Enable (MSBE) Parity Bit Enable (PBE) Even Parity Enable (EPE) Parity Bit Fixed Enable PBFE) Set Silence Enable (SSE) Baudrate Divisor Latch Access Bit (BDLAB) + 4 Handshake Control Register HCR Data Terminal Ready (DTR) Request to Send (RTS) Loopback RI Input IRQ Enable Internal Loopback Enable 0 0 0 + 5 UART Status Register USR RBR Data Ready (RDR) Overrun Error (OER) Parity Bit Error (PBER) No Stop Bit Error (NSER) Silent Byte Detected (SBD) TBR Empty (TBRE) TSR Empty (TSRE) RX FIFO Error Indication (RFEI) ** + 6 Handshake Status Register HSR CTS Toggling (TCTS) DSR Toggling (TDSR) RI Falling Edge (FERI) DCD Toggling (TDCD) Clear to Send (CTS) Data Set Ready (DSR) Ring Indicator (RI) Data Carrier Detect (DCD) + 7 User Defined Register UDR Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 + 0 BDLAB = 1 Baudrate Divisor Latch Low BLL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 + 1 BDLAB = 1 Baudrate Divisor Latch High BHL Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode. |
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