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W83977EF-AW Datasheet(PDF) 4 Page - Winbond |
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W83977EF-AW Datasheet(HTML) 4 Page - Winbond |
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4 / 142 page  W83977EF-AW/W83977EG-AW Publication Release Date: Apr. 2006 -III- Revision 1.2 6.2.6 Interrupt Status Register (ISR) (Read only)..................................................................50 6.2.7 Interrupt Control Register (ICR) (Read/Write) ..............................................................51 6.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write).............................................51 6.2.9 User-defined Register (UDR) (Read/Write) ..................................................................52 7. PARALLEL PORT .................................................................................................................... 53 7.1 Printer Interface Logic................................................................................................... 53 7.2 Enhanced Parallel Port (EPP) ...................................................................................... 54 7.2.1 Data Swapper...............................................................................................................55 7.2.2 Printer Status Buffer .....................................................................................................55 7.2.3 Printer Control Latch and Printer Control Swapper.......................................................56 7.2.4 EPP Address Port ........................................................................................................56 7.2.5 EPP Data Port 0-3........................................................................................................57 7.2.6 Bit Map of Parallel Port and EPP Registers..................................................................57 7.2.7 EPP Pin Descriptions ...................................................................................................58 7.2.8 EPP Operation .............................................................................................................58 7.3 Extended Capabilities Parallel (ECP) Port ................................................................... 59 7.3.1 ECP Register and Mode Definitions .............................................................................59 7.3.2 Data and ecpAFifo Port ................................................................................................60 7.3.3 Device Status Register (DSR) ......................................................................................60 7.3.4 Device Control Register (DCR).....................................................................................61 7.3.5 CFIFO (Parallel Port Data FIFO) Mode = 010 ..............................................................62 7.3.6 ECPDFIFO (ECP Data FIFO) Mode = 011...................................................................62 7.3.7 TFIFO (Test FIFO Mode) Mode = 110..........................................................................62 7.3.8 CNFGA (Configuration Register A) Mode = 111...........................................................62 7.3.9 CNFGB (Configuration Register B) Mode = 111...........................................................62 7.3.10 ECR (Extended Control Register) Mode = all ...............................................................63 7.3.11 Bit Map of ECP Port Registers .....................................................................................64 7.3.12 ECP Pin Descriptions ...................................................................................................65 7.3.13 ECP Operation .............................................................................................................66 7.3.14 FIFO Operation ............................................................................................................66 7.3.15 DMA Transfers .............................................................................................................67 7.3.16 Programmed I/O (NON-DMA) Mode.............................................................................67 7.4 Extension FDD Mode (EXTFDD).................................................................................. 67 7.5 Extension 2FDD Mode (EXT2FDD).............................................................................. 67 8. KEYBOARD CONTROLLER .................................................................................................... 68 8.1 Output Buffer................................................................................................................. 68 8.2 Input Buffer ................................................................................................................... 68 8.3 Status Register ............................................................................................................. 69 8.4 Commands.................................................................................................................... 70 8.5 Hardware GATEA20/Keyboard Reset Control Logic................................................... 71 8.5.1 KB Control Register (Logic Device 5, CR-F0)...............................................................71 8.5.2 Port 92 Control Register (Default Value = 0x24) ..........................................................72 |
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