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RV5C387A Datasheet(PDF) 41 Page - RICOH electronics devices division |
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RV5C387A Datasheet(HTML) 41 Page - RICOH electronics devices division |
41 / 49 page 41 RV5C387A Setting CTFG bit to 0 (Increment of second counter) (Increment of second counter) (Increment of second counter) CTFG bit INTRA pin Setting CTFG bit to 0 • Level Mode Approx. 92 µs CTFG bit INTRA pin (Increment of second counter) Rewriting of the second counter Relation Between the Mode Waveform and the CTFG Bit • Pulse Mode *) In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTRA pin low. 5. 32-kHz Clock Output 32.768-kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the control register 2 or the CLEN2 bit in the control register 1 is set to 0. If the conditions described above are not satisfied, the output is set to high. CLEN1 CLEN2 32KOUT pin output (D3 at Address Fh) (D4 at Address Eh) (Nch Open Drain output) 11 OFF(“H”) 0 (Default) * Clock pulses * 0 (Default) The 32KOUT pin output is synchronized with the CLEN1, CLEN2 bit, settings as illustrated in the timing chart below. MAX. 61.0 µs MAX. 45.8 µs 32KOUT pin CLEN1 or CLEN2 |
Similar Part No. - RV5C387A_03 |
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Similar Description - RV5C387A_03 |
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