RV5C387A_03 datasheet(38/49 Pages) RICOH

Part #	RV5C387A

Description	I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION

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Manufacturer	RICOH [RICOH electronics devices division]

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RV5C387A

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4. Alarm and Periodic Interrupt

The RV5C387A incorporates the alarm circuit and the periodic interrupt circuit that are configured to generate

alarm signals and periodic interrupt signals, respectively, for output from the INTRB or INTRC pin as described below.

1) Alarm Circuit

The alarm interrupt circuit is configured to generate alarm signals for output from the INTRB or INTRC, which

is driven low (enabled) upon the occurrence of a match between current time read by the time counters (the day-

of-week, hour, and minute counters) and alarm time preset by the alarm registers (the Alarm_W registers

intended for the day-of-week, hour, and minute digit settings and the Alarm_D registers intended for the hour

and minute digit settings). The Alarm_W is output form the INTRB pin, and the Alarm_D is output from INTRC

pin.

2) Periodic Interrupt Circuit

The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals

in the level mode for output from the INTRA pin depending on the CT2, CT1, and CT0 bit settings in the control

register 1.

The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the

control register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the

control register 1) as listed in the table below.

Flag Bits

Enable Bits

Output Pin

Alarm signals

WAFG bit

WALE bit

INTRB

(under control of Alarm_W registers)

(D1 at address Fh)

(D7 at address Eh)

Alarm signals

DALE bit

INTRC

(under control of Alarm_D registers)

(D0 at address Fh)

(D6 at address Eh)

Periodic interrupt signals

CTFG bit

CT2, CT1, and CT0 bits (D2 to D0 at address Eh)

INTRA

(D2 of Internal Address Fh) (these bit settings of 0 disable the periodic interrupt circuit)

· At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the control register 1, the INTRA,

INTRB or INTRC pin is driven high (disabled).

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RV5C387A Datasheet(PDF) 38 Page - RICOH electronics devices division

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