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RV5C387A Datasheet(PDF) 36 Page - RICOH electronics devices division

Part # RV5C387A
Description  I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION
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Manufacturer  RICOH [RICOH electronics devices division]
Direct Link  http://www.ricoh.com
Logo RICOH - RICOH electronics devices division

RV5C387A Datasheet(HTML) 36 Page - RICOH electronics devices division

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RV5C387A
36
3. Oscillation Halt Sensing and Supply Voltage Monitoring
The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The
supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or
1.6 volts. For these functions, the real-time clock has two flag bits (ie. the XSTP bit for the former and the VDET bit
for the latter) in which 1 is set once and this setting is maintained until 0 is written.
When the XSTP bit is set to 1 for the oscillation halt sensing circuit, the VDET bit is reset to 0 for the supply voltage
monitoring circuit. The relationship between the XSTP and VDET bits is shown in the table below.
XSTP
VDET
Conditions of supply voltage and oscillation
00
No drop in supply voltage below threshold voltage and no halt in oscillation
01
Drop in supply voltage below threshold voltage and no halt in oscillation
1
*
Halt on oscillation
Supply voltage
Threshold voltage (2.1 or 1.6 volts)
Setting XSTP and
VDET bits to 0
Setting XSTP and
VDET bits to 0
Internal initialization
period
(1 to 2 seconds)
Setting VDET bit to 0
Oscillation by 32.768-kHz clock pulses
Normal voltage detector
Supply voltage monitoring (VDET)
Oscillation halt sensing (XSTP)
When the XSTP bit is set to 1 in the control register 2, the F6 to F0, WALE, DALE, CLEN2, 12/24, TEST, CT2, CT1,
CT0, VDSL, VDET, SCRATCH, CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment
register, the control register 1, and the control register 2. The XSTP bit is also set to 1 at power-on from 0 volts. Note
that the XSTP bit may be locked to 0 and the internal register broken upon instantaneous power-down.


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