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RV5C387A Datasheet(PDF) 22 Page - RICOH electronics devices division |
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RV5C387A Datasheet(HTML) 22 Page - RICOH electronics devices division |
22 / 49 page RV5C387A 22 USAGES 1. Interfacing with the CPU The RV5C387A employs the I 2C bus system to be connected to the CPU via 2-wires. Connection and transfer system of I 2C bus are described in the following sections. Note I 2C bus is a trademark of PHILIPS ELECTRONICS N.V. 1.1 Connection of I 2C bus 2-wires, SCL and SDA which are connected to I 2C bus are used for transmit clock pulses and data respectively. All ICs that are connected to these lines are designed that will be not be clamped when a voltage beyond supply voltage is applied to input or output pins. Open drain pins are used for output. This construction allows communication of signals between ICs with different supply voltages by adding a pull-up resistor to each signal line as shown in the figure below. Each IC is designed not to affect SCL and SDA signal lines when power to each of these is turned off separately. VDD1 VDD2 VDD3 VDD4 SCL RP RP SDA Microcontroller RV5C387A Other Peripheral Device *1) For data interface, the following conditions must be met: VDD4 ≥VDD1 VDD4 ≥VDD2 VDD4 ≥VDD3 *2) When the master is one, the micro controller is ready for driving SCL to “H” and RP of SCL may not be required. |
Similar Part No. - RV5C387A_03 |
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Similar Description - RV5C387A_03 |
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