13

RV5C387A

Relation Between the Mode Waveform and the CTFG Bit

• Pulse mode

Approx. 92

µs

CTFG bit

INTRA pin

(Increment of second counter)

Rewriting of the second counter

• Level mode

Setting CTFG bit to 0

(Increment of

second counter)

(Increment of

second counter)

(Increment of

second counter)

CTFG bit

INTRA pin

Setting CTFG bit to 0

readings immediately after the falling edge of clock pulses may appear to lag behind the time counts of the real-time clocks by approximately 1 second.

Rewriting the second counter will reset the other time counters of less than 1 second, driving the INTRA pin low.