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PS12036 Datasheet(PDF) 5 Page - Mitsubishi Electric Semiconductor |
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PS12036 Datasheet(HTML) 5 Page - Mitsubishi Electric Semiconductor |
5 / 5 page MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12036 FLAT-BASE TYPE INSULATED TYPE Mar. 2002 SC Ic(A) OC tw ( µs) Over current trip level Collector current Short circuit trip level 10 2 0 CURRENT ABNORMALITY PROTECTIVE FUNCTIONS ARM-SHOOT-THROUGH INTER-LOCK PROTECTIVE FUNCTION Protection is achieved by monitoring and filtering the N-side DC-Bus current. When a current trip-level is exceeded all the N-side IGBTs are intercepted (turned OFF) and a fault-signal is output. After the fault-sig- nal output duration (1.8m sec (typ.)@25 °C), the interception is Reset at the following OFF input signal level (more than 4.0V). (Fig. 5) P-Side Input Signal : VCIN(p) N-Side Input Signal : VCIN(n) ON ON P-Side IGBT Gate : VGE(p) N-Side IGBT Gate : VGE(n) a1 b4 b3 b2 b1 a4 a3 a2 0 0 (Fig. 6) Description: (1) During the ON-State of either of the upper-arm or the lower-arm IGBT, the inter-lock protection circuit blocks any erroneous ON pulses (re- sulting from input noise) from triggering the other arm IGBT and thus it prevents the arm-shoot-through situation. (2) When two ON-signals are received for both the upper and the lower arms, the signal received first will be passed to the IGBT and the sec- ond signal will be blocked. The second signal will be passed to its corresponding IGBT immediately after the first signal is OFF. Note: This protective function provides no fault signaling output. The Dead-Time has to be set using the micro-controller (CPU). b1. N-side normal ON-signal ⇒ N-side IGBT gate turns ON. b2. Simultaneous ON-signals ⇒ P-side IGBT gate remains OFF. b3. N-side receives OFF-signal ⇒ N-side IGBT gate turns OFF. b4. Immediately after (b3) ⇒ P-side IGBT gate turns ON. Operation: a1. P-side normal ON-signal ⇒ P-side IGBT gate turns ON. a2. N-side erroneous ON-signal ⇒ N-side IGBT gate remains OFF. a3. While P-side ON-signal remains ⇒ P-side IGBT gate remains ON. a4. N-side normal ON-signal ⇒ N-side IGBT gate turns ON. RECOMMENDED I/O INTERFACE CIRCUIT (Fig. 7) FO Vamp GND ASIPM 5V 5V VD(15V) CPU 5.1k Ω 10k Ω 0.1nF Up, Vp, Wp, Un, Vn, Wn |
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