LC87F06J2A

No.A0432-19/32

4. SIO7, SIO8 Serial I/O Characteristics (Note 4-4-1)

Specification

Parameter

Symbol

Pins/

Remarks

Conditions

VDD[V]

min

typ

max

uni

Frequency

tSCK(7)

2

Low level

pulse width

tSCKL(7)

1

High level

pulse width

tSCKH(7)

SCK7(PA2),

SCK8(PA5)

• See Fig. 6.

• (Note 4-4-2)

2.7 to 5.5

1

Frequency

tSCK(8)

4/3

tCYC

Low level

pulse width

tSCKL(8)

1/2

tSCKH(8)

1/2

High level

pulse width

tSCKHA(8)

SCK7(PA2),

SCK8(PA5)

• CMOS output selected.

• See Fig. 6.

2.7 to 5.5

1.5

tSCK

Data setup time

tsDI(4)

0.03

Data hold time

thDI(4)

SI7(PA1),

SB7(PA1),

SI8(PA4),

SB8(PA4)

• Must be specified with respect

to rising edge of SIOCLK

• See fig. 6.

2.7 to 5.5

0.03

tdDO(6)

1tCYC

+0.05

Output delay

time

tdDO(7)

SO7(PA0),

SB7(PA1),

SO8(PA3),

SB8(PA4)

• Must be specified with respect

to falling edge of SIOCLK

• Must be specified as the time

to the beginning of output state

change in open drain output

mode.

• See Fig. 6.

2.7 to 5.5

(1/3)tCYC

+0.05

µs

Note 4-4-1: These specifications are theoretical values. Add margin depending on its use.

Note 4-4-2: When starting transmission/reception of SIO7(SIO8) using serial-clock-input, a time from

SI7RUN(SI8RUN) being set when serial clock is "H" to the first negative edge of the serial clock must be

longer than 1tCYC.