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LC87F06J2A Datasheet(PDF) 18 Page - Sanyo Semicon Device |
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LC87F06J2A Datasheet(HTML) 18 Page - Sanyo Semicon Device |
18 / 32 page LC87F06J2A No.A0432-18/32 3. SIO2 Serial I/O Characteristics (Note 4-3-1) Specification Parameter Symbol Pins/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(5) 2 Low level pulse width tSCKL(5) 1 tSCKH(5) • See Fig. 6. 1 tSCKHA(5a) • Continuous data transmission/reception mode of SIO0 is not in use simultaneous. • Universal remote control transmitter is not in use simultaneous. • See Fig. 6. • (Note 4-3-2) 4 High level Pulse width tSCKHA(5b) SCK2 (SI2P2) • Continuous data transmission/reception mode of SIO0 is in use simultaneous. • Universal remote control transmitter is in use simultaneous. • See Fig. 6. • (Note 4-3-2) 2.7to 5.5 10 Frequency tSCK(6) 4/3 tCYC Low level pulse width tSCKL(6) 1/2 tSCKH(6) • CMOS output selected. • See Fig. 6. 1/2 tSCK tSCKHA(6a) • Continuous data transmission/reception mode of SIO0 is not in use simultaneous. • Universal remote control transmitter is not in use simultaneous. • CMOS output selected. • See Fig. 6. tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC High level pulse width tSCKHA(6b) SCK2 (SI2P2), SCK2O (SI2P3) • Continuous data transmission/reception mode of SIO0 is in use simultaneous. • Universal remote control transmitter is in use simultaneous. • CMOS output elected. • See Fig. 6. 2.7 to 5.5 tSCKH(6) +(5/3) tCYC tSCKH(6) +(28/3) tCYC tCYC Data setup time tsDI(3) 0.03 Data hold time thDI(3) SI2(SI2P1), SB2(SI2P1) • Must be specified with respect to rising edge of SIOCLK • See fig. 6. 2.7 to 5.5 0.03 Output delay time tdDO(5) SO2(SI2P0) SB2(SI2P1) • Must be specified with respect to falling edge of SIOCLK • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 6. 2.7 to 5.5 (1/3)tCYC +0.05 µs Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. |
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