LC87F06J2A

No.A0432-14/32

Continued from preceding page.

Specification

Parameter

Symbol

Pins/Remarks

Conditions

VDD[V]

min

typ

max

unit

VIL(1)

Ports 1, 2, 3,A

PB6

SI2P0 to SI2P3

P71 to P73

P70 port input /interrupt

2.7 to 5.5

VSS

0.1VDD

+0.4

VIL(2)

Ports 0, 8

PB0 to PB2, PB4

Ports C, E, F

PWM0,PWM1

2.7 to 5.5

VSS

0.15VDD

+0.4

VIL(3)

Port 70 Watchdog

Timer

2.7 to 5.5

VSS

0.8VDD

-1.0

VIL(4)

XT1, XT2, CF1,

RES

2.7 to 5.5

VSS

0.25VDD

Low level

input voltage

VIL(5)

P20, P24 Small signal

input side

2.7 to 5.5

VSS

0.25VDD

V

VCVD(1)

2Vp-p input mode

5.0

1.4

2.0

2.6

Composite

video signal

input voltage

(Note 2-4)

VCVD(2)

PB6(CVD)

1Vp-p input mode

5.0

0.7

1

1.3

Vp-p

Data-slicer Operating mode

4.75 to 5.25

0.196

0.340

4.5 to 5.5

0.196

200

Instruction

cycle time

(Note 2-2)

tCYC

2.7 to 5.5

1.470

200

µs

FmCF(1)

CF1, CF2

15MHz ceramic oscillation

See Fig. 1.

4.5 to 5.5

15

FmRC

Internal RC oscillation

2.7 to 5.5

0.3

1.0

2.0

FmMRC

Frequency variable RC

oscillation source oscillation

2.7 to 5.5

16

MHz

Oscillation

frequency

Range

(Note 2-3)

FsX’tal

XT1, XT2

32.768kHz crystal oscillation.

See Fig. 2.

2.7 to 5.5

32.768

kHz

Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at

a division ratio of 1/2.

Note 2-3: See Tables 1 and 2 for the oscillation constants.

Note 2-4: When setting DSLDACT register’s bit7 = 0, bit6 = 0. See diagram 9 for external circuit.