LC87F06J2A

No.A0432-13/32

Continued from preceding page.

Specification

Parameter

Symbol

Pins/Remarks

Conditions

VDD[V]

min

typ

max

unit

ΣIOAL(1)

Port 7, XT2

Total of all applicable pins

15

ΣIOAL(2)

Port 8

Total of all applicable pins

15

ΣIOAL(3)

Ports 7, 8, XT2

Total of all applicable pins

30

ΣIOAL(4)

PWM0, PWM1

SI2P0 to SI2P3

Total of all applicable pins

40

ΣIOAL(5)

Ports 0, 2, 3

Total of all applicable pins

80

ΣIOAL(6)

Ports 0, 2, 3

PWM0, PWM1

SI2P0 to SI2P3

Total of all applicable pins

120

ΣIOAL(7)

PB0 to PB2

Total of all applicable pins

40

ΣIOAL(8)

Ports A, C

Total of all applicable pins

40

ΣIOAL(9)

Ports A, C

PB0 to PB2

Total of all applicable pins

80

ΣIOAL(10)

Port F

Total of all applicable pins

40

ΣIOAL(11)

Ports 1, E

Total of all applicable pins

70

ΣIOAL(12)

Ports 1, E, F

Total of all applicable pins

110

Total output

current

ΣIOAL(13)

PB4, PB6

Total of all applicable pins

40

mA

Maximum power

consumption

Pd max

QIP100E(14

×20)

523

mW

Operating

temperature range

Topr

-20

70

Storage

temperature range

Tstg

-55

125

°C

Recommended Operating Range at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V

Specification

Parameter

Symbol

Pins/Remarks

Conditions

VDD[V]

min

typ

max

unit

0.196µs

≤ tCYC ≤ 200µs

4.5

5.5

Operating

supply voltage

(Note 2-1, 2-2)

VDD(1)

VDD1=VDD2

=VDD3=VDD4

=VDDVCO=VDDODA

1.47µs

≤ tCYC ≤ 200µs

2.7

5.5

Data-slicer

Operating

supply voltage

VDD(2)

VDD1=VDD2

=VDD3=VDD4

=VDDVCO=VDDODA

0.196µs

≤ tCYC ≤ 0.340µs

4.75

5.25

Base timer

Day and time

counter

Operating

supply voltage

VDD(3)

VDD1

• X’tal HOLD mode

• Base timer clock is subclock.

• FsX’tal=32.768kHz by crystal

oscillation mode.

2.0

5.5

Memory

sustaining

supply voltage

VHD

VDD1

RAM and register contents in

HOLD mode.

2.0

5.5

VIH(1)

Ports 1, 2, 3, A

PB6

SI2P0 to SI2P3

P71 to P73

P70 port input /interrupt

side

2.7 to 5.5

0.3VDD

+0.7

VDD

VIH(2)

Ports 0, 8

PB0 to PB2, PB4

Ports C, E, F

PWM0, PWM1

2.7 to 5.5

0.3VDD

+0.7

VDD

VIH(3)

P70 Watchdog timer side

2.7 to 5.5

0.9VDD

VDD

VIH(4)

XT1, XT2, CF1, RES

2.7 to 5.5

0.75VDD

VDD

High level

input voltage

VIH(5)

P20, P24 Small signal

input side

2.7 to 5.5

0.75VDD

VDD

V

Note 2-1: VDD must be held greater than or equal to 4.5V in the flash ROM onboard programming mode.

Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at

a division ratio of 1/2.

Continued on next page.