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75N42102 Datasheet(PDF) 1 Page - Integrated Device Technology |
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75N42102 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 3 page ![]() APRIL 2004 DSC-6457/00 1 2004 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. NETWORK SEARCH ENGINE 32K x 72 Entries Datasheet Brief 75N42102 Device Description IDT provides proven, industry-leading network search engines (NSEs) that enable and accelerate the intelligent processing of network services in communications equipment. As a part of the complete IDT classificationsubsystemthatincludescontentinspectionengines,theIDT family of NSEs delivers high-performance, feature-rich, easy-to-use, integrated search accelerators. TheIDT 75N42102NSEisahighperformance,lowcost, full-ternary 32K x 72 entry device. Each entry location in the NSE has both a Data entry and an associated Mask entry. The NSE devices integrate content addressable memory (CAM) technology with high-performance logic. The device can perform Lookup operations plus Read and Write maintenanceoperations. The IDT 75N42102 NSE device has a bi-directional bus that is a multiplexed address and data bus that can support up to 200 million sustained searches per second. This device offers the ability to simulta- neouslysearchinmutuallyexclusivedatabasessubstantiallyincreasing the NSE search rate. This device can be configured to enable multiple width lookups from 40 to 288 bits wide. The IDT 75N42102 requires a 1.5-volt VDD1 supply and a 2.5-volt VDD2 supply. The IDT 75N42102 NSE utilizes the latest high-performance 1.5V CMOS processing technology and is packaged in a JEDEC Standard, thermally enhanced, 304 pin low profile Ball Grid Array. To request the full IDT75N42102 datasheet, please contact your local IDT Sales Representative or call 1-800-345-7015 6457 drw02 Optional Figure 1.0 ASIC / Compatible NSE / SRAM configuration ASIC or FPGA ZBT or Sync SRAM IDT 75N42102 Network Search Engine Configuration Registers and Ram Control Circuits CLOCK CCLK ÷2 PHASE SRAM CONTROL P R I O R I T Y E N C O D E R S I Z E L O G I C D E C O D E Address MATCHOUT REQSTB R/W 6457 drw 01 RESET Command Bus Request Data Bus Index Bus NSE REQUEST BUS NSE RESPONSE BUS MATCHIN CONFIGIN ASIC FEEDBACK Bypass DATA ARRAY Instruction Global Mask Registers Result Register CONFIGOUT Block Diagram System Configurations The IDT NSEs are designed to fulfill the needs of various types of networking systems. In solutions requiring data searching such as routers, a system configuration as shown in Figure 1.0 may be realized. In this configuration, the NSE interfaces directly to an ASIC/ FPGA for lookups and routes an Index to an associated SRAM device, which supplies the next hop address via an SRAM Data Bus to the ASIC. The NSE provides the required control signals to directly hookup to ZBT™ or Synchronous Pipeline Burst SRAM. Lookup results can also be fed directlybacktotheASIC/FPGAwithouttheuseofexternalSRAM.Control of the associated handshake signals is provided by all NSEs to adapt to eitherconfiguration. |
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