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75N42102 Datasheet(PDF) 3 Page - Integrated Device Technology |
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75N42102 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 3 page 6.42 3 Network Search Engine 32K x 72 Entries Datasheet Brief 75N42102 Signal Descriptions Pin Function I/O Description NSE Request Bus: Request Strobe Input This input signifies a valid input request and signals the start of an NSE operation cycle. Command Bus Input Defines the instruction to be performed by the NSE and selects Glo bal Mask registers and Search Result registers. Request Data Bus Input/Output Three State The Request Data Bus is a multiplexed address/data bus used to perform reads (and writes) from (to) the NSE, and to present search data for lookups. NSE Response Bus: Index Bus Output Three State This bus is used to drive the address of an ex ternal SRAM, or feedback Lookup result information directly to the NSE's ASIC/FPGA. The Index Bus contains the encoded location at which the compare was found. Chip Enable/ Output Enable Output Three State This signal is driven along with the Index Bus. It is connected to the CE input pin of a ZBT SRAM or to the OE pin of a PBSRAM. Write Enable Output Three State This signal is driven along with the Index bus. It is used to assert the WE pin of an external SRAM. It is active for SRAM write operations. Read Acknowledge Output This signal is sent back when the data is read from the NSE on the Request Data Bus, or when the data being read from the associated external SRAM. Match Acknowledge Output This is signal is sent with the Index. It will be driven low if there was no match, high if a match was found. Valid Lookup Bit Output This signal is sent with the Index. It will be driven high upon the completion of a lookup, even if the lookup did not result in a hit. Clock and Initialization: Clock Input Input All inputs and outputs are referenced to the positive edge of this clock. Clock Phase Enable Input This signal is used to generate an internal clock at ½ the freque ncy of the input clock. Reset Input This pin will force all outputs to a high impedence condition, as well as clearing the NSE enable bit. Depth Expansion: Configuration In Input Configures the Device ID at power up. Configuration Out Output Configures the Device ID at power up. Match Input Input The Match Input signal is driven by all upstream Match Output signals. This indicates to all down stream NSEs that a hit in a higher priority NSE has occurred. Match Output Output The Match Output signal signifies that a match has occurred in the NSE. The signal is fed into a Match Input line of all lower priority NSE(s). 6457 tbl 01 |
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