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PT0222(02/06)

Ver: 0

8

Data Sheet

PT7C4300

Real-time Clock Module (I

Addr.

(hex)

Description

D7

D6

D5

D4

D3

D2

D1

D0

Dates (01-31)

×

×

D20

D10

D8

D4

D2

D1

04

(default)

Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

Months (01-12)

×

×

×

M10

M8

M4

M2

M1

05

(default)

Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

Years (00-99)

Y80

Y40

Y20

Y10

Y8

Y4

Y2

Y1

06

(default)

Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

Communication

1.

I

a)

Overview of I

The I

of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on.

Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and

stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data

transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the

data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per

clock pulse. The I

chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its

slave address matches the slave address in the received data.

b)

System Configuration

All ports connected to the I

multiple devices.

SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high

level when the bus is released (when communication is not being performed).

Master

MC U

Slave

RTC

O ther Peripheral

Device

Vcc

SD A

SC L

N ote: W hen there is only one m aster, the M C U is ready for driving SC L to "H " and R

R

P

R

P

Fig.1 System configuration