M58WR064T datasheet(20/81 Pages) STMICROELECTRONICS

Part #	M58WR064T

Description	64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory

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M58WR064T, M58WR064B

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formance is possible. Typical Program times are

given in Table 14.

The Enhanced Factory Program command has

four phases: the Setup Phase, the Program Phase

to program the data to the memory, the Verify

Phase to check that the data has been correctly

programmed and reprogram if necessary and the

Exit Phase. Refer to Table 7, Enhanced Factory

Program Command and Figure 26, Enhanced

Factory Program Flowchart.

Setup Phase. The Enhanced Factory Program

command requires two Bus Write operations to ini-

tiate the command.

s

The first bus cycle sets up the Enhanced

Factory Program command.

s

The second bus cycle confirms the command.

The Status Register P/E.C. Bit 7 should be read to

check that the P/E.C. is ready. After the confirm

command is issued, read operations output the

Status Register data. The read Status Register

command must not be issued as it will be

interpreted as data to program.

Program Phase. The Program Phase requires

n+1 cycles, where n is the number of Words (refer

to Table 7, Enhanced Factory Program Command

and Figure 26, Enhanced Factory Program Flow-

chart).

Three successive steps are required to issue and

execute the Program Phase of the command.

1. Use one Bus Write operation to latch the Start

Address and the first Word to be programmed.

The Status Register Bank Write Status bit SR0

should be read to check that the P/E.C. is ready

for the next Word.

2. Each subsequent Word to be programmed is

latched with a new Bus Write operation. The

address can either remain the Start Address, in

which case the P/E.C. increments the address

location or the address can be incremented in

which case the P/E.C. jumps to the new

address. If any address that is not in the same

block as the Start Address is given with data

FFFFh, the Program Phase terminates and the

Verify Phase begins. The Status Register bit

SR0 should be read between each Bus Write

cycle to check that the P/E.C. is ready for the

next Word.

3. Finally, after all Words have been programmed,

write one Bus Write operation with data FFFFh

to any address outside the block containing the

Start Address, to terminate the programming

phase. If the data is not FFFFh, the command is

ignored.

The memory is now set to enter the Verify Phase.

Verify Phase. The Verify Phase is similar to the

Program Phase in that all Words must be resent to

the memory for them to be checked against the

programmed data. The Program/Erase Controller

checks the stream of data with the data that was

programmed in the Program Phase and repro-

grams the memory location if necessary.

Three successive steps are required to execute

the Verify Phase of the command.

1. Use one Bus Write operation to latch the Start

Address and the first Word, to be verified. The

Status Register bit SR0 should be read to check

that the Program/Erase Controller is ready for

the next Word.

2. Each subsequent Word to be verified is latched

with a new Bus Write operation. The Words

must be written in the same order as in the

Program Phase. The address can remain the

Start Address or be incremented. If any address

that is not in the same block as the Start

Address is given, the Verify Phase terminates.

Status Register bit SR0 should be read to check

that the P/E.C. is ready for the next Word.

3. Finally, after all Words have been verified, write

one Bus Write operation with data FFFFh to any

address outside the block containing the Start

Address, to terminate the Verify Phase.

If the Verify Phase is successfully completed the

memory returns to the Read mode. If the Program/

Erase Controller fails to reprogram a given loca-

tion, the Verify Phase will terminate, the error will

be signaled in the Status Register and the memory

will output the Status Register until a Read/Reset

command is issued.

Exit Phase. Status Register P/E.C. bit SR7 set to

‘1’ indicates that the device has returned to Read

Array mode. A full Status Register check should

be done to ensure that the block has been suc-

cessfully programmed. See the section on the Sta-

tus Register for more details.

Quadruple Enhanced Factory Program

Command

The Quadruple Enhanced Factory Program com-

mand can be used to program one or more pages

of four adjacent words in parallel. The four words

must differ only for the addresses A0 and A1. VPP

must be set to VPPH during Quadruple Enhanced

Factory Program.

It has four phases: the Setup Phase, the Load

Phase where the data is loaded into the buffer, the

combined Program and Verify Phase where the

loaded data is programmed to the memory and

then automatically checked and reprogrammed if

necessary and the Exit Phase. Unlike the En-

hanced Factory Program it is not necessary to re-

submit the data for the Verify Phase. The Load

Phase and the Program and Verify Phase can be

repeated to program any number of pages within

the block.

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