4

February, 2007

Document Control #ML0018 Rev 0.3

STK16C88

SRAM READ CYCLES #1 & #2

Note f:

W must be high during SRAM READ cycles and low during SRAM WRITE cycles.

Note g:

Note h:

Measured + 200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Controlledf, g

SRAM READ CYCLE #2: E Controlledf

NO.

SYMBOLS

PARAMETER

STK16C88-25

STK16C88-45

UNITS

#1, #2

Alt.

MIN

MAX

MIN

MAX

1

Chip Enable Access Time

25

45

ns

2

f

Read Cycle Time

25

45

ns

3

g

Address Access Time

25

45

ns

4

Output Enable to Data Valid

10

20

ns

5

g

Output Hold after Address Change

5

5

ns

6

Chip Enable to Output Active

5

5

ns

7

h

Chip Disable to Output Inactive

10

15

ns

8

Output Enable to Output Active

0

0

ns

9

h

Output Disable to Output Inactive

10

15

ns

10

e

Chip Enable to Power Active

0

0

ns

11

d, e

Chip Disable to Power Standby

25

45

ns

DATA VALID

5

3

DQ (DATA OUT)

ADDRESS

2

STANDBY

DATA VALID

DQ (DATA OUT)

E

ADDRESS

2

G

ACTIVE

1

11

7

9

6

8

4

10