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STK14C88-3 Datasheet(PDF) 5 Page - Simtek Corporation |
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STK14C88-3 Datasheet(HTML) 5 Page - Simtek Corporation |
5 / 17 page ![]() 5 STK14C88-3 February 2007 Document Control #ML0015 Rev 0.6 SRAM READ CYCLES #1 & #2 (VCC = 3V - 3.6V) e Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note h: /O state assumes E and G < VIL and W > VIH; device is continuously selected. Note i: Measured ± 200mV from steady state output voltage. NO. SYMBOLS PARAMETER STK14C88-3-35 STK14C88-3-45 UNITS #1, #2 Alt. MIN MAX MIN MAX 1 tELQV tACS Chip Enable Access Time 35 45 ns 2 tAVAVg tRC Read Cycle Time 35 45 ns 3 tAVQVh tAA Address Access Time 35 45 ns 4 tGLQV tOE Output Enable to Data Valid 15 20 ns 5 tAXQXh tOH Output Hold after Address Change 5 5 ns 6 tELQX tLZ Chip Enable to Output Active 5 5 ns 7 tEHQZi tHZ Chip Disable to Output Inactive 13 15 ns 8 tGLQX tOLZ Output Enable to Output Active 0 0 ns 9 tGHQZi tOHZ Output Disable to Output Inactive 13 15 ns 10 tELICCHf tPA Chip Enable to Power Active 0 0 ns 11 tEHICCLf tPS Chip Disable to Power Standby 35 45 ns SRAM READ CYCLE #1: Address Controlledg, h DATA VALID 5 tAXQX 3 tAVQV DQ (DATA OUT) ADDRESS 2 tAVAV SRAM READ CYCLE #2: E Controlledg 6 tELQX STANDBY DATA VALID 4 tGLQV DQ (DATA OUT) E ADDRESS 2 tAVAV G ICC ACTIVE 10 tELICCH 11 tEHICCL 7 tEHQZ 8 tGLQX 1 tELQV 9 tGHQZ |
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