6

February, 2007

Document Control #ML0014 Rev 0.3

STK14C88

HARDWARE MODE SELECTION

Note m: HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes,

the part will go into standby mode, inhibiting all operations until HSB rises.

HARDWARE STORE CYCLE

e

Note n:

E and G low and W high for output behavior.

Note o:

HARDWARE STORE CYCLE

E

W

HSB

MODE

I/O

POWER

NOTES

H

X

H

X

Not Selected

Output High Z

Standby

L

H

H

X

Read SRAM

Output Data

Active

t

L

L

H

X

Write SRAM

Input Data

Active

X

X

L

X

Nonvolatile

STORE

Output High Z

m

NO.

SYMBOLS

PARAMETER

STK14C88

UNITS

NOTES

Standard

Alternate

MIN

MAX

22

STORE Cycle Duration

10

ms

i, n

23

Time Allowed to Complete SRAM Cycle

1

μsi, n

24

Hardware STORE High to Inhibit Off

700

ns

n, o

25

Hardware STORE Pulse Width

15

ns

26

Hardware STORE Low to STORE Busy

300

ns

DATA VALID

HSB (IN)

DATA VALID

25

23

22

24

HIGH IMPEDANCE

26

HIGH IMPEDANCE

DQ (DATA OUT)

HSB (OUT)