1996 Aug 23

7

Philips Semiconductors

Product specification

8-bit video digital-to-analog converter

TDA8702

Note

3. The

−3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input

code transition (code 0 to 255).

4. The worst case characteristics are obtained at the transition from input code 0 to 255 and if an external load

impedance greater than 75

been applied. All input data is latched at the rising edge of the clock. The output voltage remains stable (independent

of input data variations) during the HIGH level of the clock (CLK = HIGH). During a LOW-to-HIGH transition of the

clock (CLK = LOW), the DAC operates in the transparent mode (input data will be directly transferred to their

corresponding analog output voltages (see Fig.5).

stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the rising

of the clock that the input data must be stable in order to be correctly registered. A negative hold time indicates that

the data may be released prior to the rising edge of the clock and still be recognized.

6. The definition of glitch energy and the measurement set-up are shown in Fig.6. The glitch energy is measured at the

input transition between code 127 to 128 and on the falling edge of the clock.

data set-up time

−0.3

−−

ns

data hold time

2.0

−−

ns

propagation delay time

−−

1.0

ns

settling time

10% to 90% full-scale

change to

±1 LSB

−

1.1

1.5

ns

settling time

10% to 90% full-scale

change to

±1 LSB

−

6.5

8.0

ns

input to 50% output delay time

−

3.0

5.0

ns

glitch energy from code

transition 127 to 128

−−

30

LSB.ns

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT