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TDA4853 Datasheet(PDF) 37 Page - NXP Semiconductors |
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TDA4853 Datasheet(HTML) 37 Page - NXP Semiconductors |
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37 / 60 page  1999 Jul 13 37 Philips Semiconductors Product specification I2C-bus autosync deflection controllers for PC/TV monitors TDA4853; TDA4854 Start-up procedure VCC < 8.3 V: • As long as the supply voltage is too low for correct operation, the IC will give no acknowledge due to internal Power-on reset (POR) • Supply current is 9 mA or less. VCC > 8.3 V: • The internal POR has ended and the IC is in standby mode • Control bits STDBY and SOFTST are reset to their start values • All other register contents are random • Pin HUNLOCK is at HIGH-level. Setting control bit STDBY = 0: • Enables internal power supply • Supply current increases from 9 to 70 mA • When VCC < 8.6 V register SOFTST cannot be set by the I2C-bus • Output stages are disabled, except the vertical output • Pin HUNLOCK is at HIGH-level. Setting all registers to defined values: • Due to the hardware configuration of the IC (no auto-increment) any register setting needs a complete 3-byte I2C-bus data transfer as follows: START - IC address - subaddress - data - STOP. Setting control bit SOFTST = 1: • Before starting the soft-start sequence a delay of minimum 80 ms is necessary to obtain correct function of the horizontal drive • HDRV duty cycle increases • BDRV duty cycle increases • PLL1 and PLL2 are enabled. IC in full operation: • Pin HUNLOCK is at LOW-level when PLL1 is locked • Any change of the register content will result in immediate change of the output behaviour • Setting control bit SOFTST = 0 is the only way (except power-down via pin VCC) to leave the operating mode. Soft-down sequence: • See L4 of Fig.21 for starting the soft-down sequence. Fig.20 I2C-bus flow for start-up. (1) See Fig.21. MGM078 START Standby mode (XXXX XX01) STDBY = 1 SOFTST = 0 all other register contents are random Protection mode (XXXX XX00) STDBY = 0 SOFTST = 0 all other register contents are random Protection mode (XXXX XX00) STDBY = 0 SOFTST = 0 registers are pre-set change/refresh of data? S 8CH A 0DH A 00H A P S 8CH A 0DH A 02H A P S 8CH A SAD A DATA A P S 8CH A SAD A DATA A P Operating mode (XXXX XX10) STDBY = 0 SOFTST = 1 Soft-start sequence (XXXX XX10) STDBY = 0 SOFTST = 1 Power-down mode (XXXX XXXX) no acknowledge is given by IC all register contents are random L1 L2 L3 L4 (1) VCC > 8.3 V no yes SOFTST = 0? no yes all registers defined? no yes |
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