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TDA4853 Datasheet(PDF) 11 Page - NXP Semiconductors |
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TDA4853 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 60 page  1999 Jul 13 11 Philips Semiconductors Product specification I2C-bus autosync deflection controllers for PC/TV monitors TDA4853; TDA4854 Vertical oscillator and amplitude control This stage is designed for fast stabilization of vertical size after changes in sync frequency conditions. The free-running frequency ffr(V) is determined by the resistor RVREF connected to pin 23 and the capacitor CVCAP connected to pin 24. The value of RVREF is not only optimized for noise and linearity performance in the whole vertical and EW section, but also influences several internal references. Therefore the value of RVREF must not be changed. Capacitor CVCAP should be used to select the free-running frequency of the vertical oscillator in accordance with the following formula: To achieve a stabilized amplitude the free-running frequency ffr(V), without adjustment, should be at least 10% lower than the minimum trigger frequency. The contributions shown in Table 2 can be assumed. Table 2 Calculation of ffr(V) total spread Result for 50 to 160 Hz application: The AGC of the vertical oscillator can be disabled by setting control bit AGCDIS via the I2C-bus. A precise external current has to be injected into VCAP (pin 24) to obtain the correct vertical size. This special application mode can be used when the vertical sync pulses are serrated (shifted); this condition is found in some display modes, e.g. when using a 100 Hz up converter for video signals. Application hint: VAGC (pin 22) has a high input impedance during scan. Therefore, the pin must not be loaded externally otherwise non-linearities in the vertical output currents may occur due to the changing charge current during scan. Adjustment of vertical size, VGA overscan and EHT compensation The amplitude of the differential output currents at VOUT1 and VOUT2 can be adjusted via register VSIZE. Register VOVSCN can activate a +17% step in vertical size for the VGA350 mode. VSMOD (pin 21) can be used for a DC controlled EHT compensation of vertical size by correcting the differential output currents at VOUT1 and VOUT2. The EW waveforms, (vertical focus), pin unbalance and parallelogram corrections are not affected by VSMOD. The adjustments for vertical size and vertical position also affect the waveforms of the horizontal pincushion, vertical linearity (S-correction), vertical linearity balance, focus parabola, pin unbalance and parallelogram correction. The result of this interaction is that no re-adjustment of these parameters is necessary after an adjustment of vertical picture size or position. Adjustment of vertical position, vertical linearity and vertical linearity balance Register VPOS provides a DC shift at the sawtooth outputs VOUT1 and VOUT2 (pins 13 and 12) and the EW drive output EWDRV (pin 11) in such a way that the whole picture moves vertically while maintaining the correct geometry. Register VLIN is used to adjust the amount of vertical S-correction in the output signal. This function can be switched off by control bit VSC. Register VLINBAL is used to correct the unbalance of the vertical S-correction in the output signal. This function can be switched off by control bit VLC. Adjustment of vertical moire cancellation To achieve a cancellation of vertical moire (also known as ‘scan moire’) the vertical picture position can be modulated by half the vertical frequency. The amplitude of the modulation is controlled by register VMOIRE and can be switched off via control bit MOD. Contributing elements Minimum frequency offset between ffr(V) and lowest trigger frequency 10% Spread of IC ±3% Spread of RVREF ±1% Spread of CVCAP ±5% Total 19% f fr V () 1 10.8 R VREF × C VCAP × ----------------------------------------------------------- = f fr V () 50 Hz 1.19 --------------- 42 Hz == |
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