AZ12010

November 2006 * REV - 5

www.azmicrotek.com

4

AZ12010 FUNCTIONAL PIN/PAD DESCRIPTIONS

Name

Functional Description

Logic Level

REFIN

Reference Frequency Input This pin/pad includes an on-chip 470

Ω pull

coupled.

REFOUT

¯¯¯¯¯¯¯¯

Reference Frequency Output This pin is an inverted and amplified version of

the signal on the REFIN pin. The gain from REFIN to REFOUT

¯¯¯¯¯¯¯¯ is

provided for the output.

REFOUT

¯¯¯¯¯¯¯¯ is not available on the packaged versions (AZ12010A, AZ12010B).

PECL

CPREF

Charge Pump Reference Output The pin/pad voltage is nominally 1.2 volts

CPOUT

during a phase correction pulse. When there is no correction pulse the output

goes high impedance.

CPPOL

Charge Pump Polarity When this pin/pad is pulled high the PLL operates

with a VCSO circuit exhibiting negative pulling slope (the VCSO frequency

goes down when the control voltage goes up). When this pin/pad is pulled low

(AZM12010B) the PLL operates with a VCSO circuit exhibiting positive

pulling slope (the VCSO frequency goes up when the control voltage goes up).

If the pin/pad is left open (AZM12010A), an internal pullup resistor selects

negative pulling slope mode.

LVCMOS

LVTTL

INTREF

Integrator Reference Input This pin/pad should be connected to CPREF

through a bias current cancellation network

INTSUM

Integrator Summing Junction This pin/pad is the summing junction for the

integrator amplifier

INTOUT

Integrator Output

SAWIN

SAWIN

¯¯¯¯¯¯¯

SAW Amplifier Inputs If only one input is used (Single-ended VCSO), the

SAWOUT

SAWOUT

¯¯¯¯¯¯¯¯

SAW Amplifier Outputs These are open collector outputs for driving the

VCSO device. Operating at nominally 9 ma, external pullup resistors must be

CML (Analog)

ENABLE

PLL Output Enable The Q and Q

¯ outputs are enabled when this pin/pad is

pulled high. When this pin/pad is low, the Q output is high, and the Q

¯ output is

low. If the pin/pad is left open, an internal pullup resistor enables the outputs.

LVCMOS

LVTTL

DIV_SEL

Divide Select When this pin/pad is high, the Q and Q

¯ outputs are divided by

one from the SAW device. When it is low, the Q and Q

¯ outputs are divided by

two from the SAW device. If the pin/pad is left open, an internal pullup resistor

selects the divide by one mode.

LVCMOS

LVTTL

Q

Q

¯

Clock Output These pin/pads are the main clock output. When ENABLE is

low, the outputs are disabled with Q high and Q

¯ low.

PECL

Reference Voltage Output This pin/pad is used to bias the REFIN signal. It

REFOUT

source is provided for the REFOUT

¯¯¯¯¯¯¯¯ output.

Positive Supply +3.0 to +3.6 V

Negative Supply Ground