3

LT1011/LT1011A

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Input Offset Voltage Drift

q

415

4

25

µV/°C

∆T

(Note 6)

*Large-Signal Voltage Gain

200

500

200

500

V/mV

–10V

50

300

50

300

V/mV

0.5V

CMRR

Common Mode

94

115

90

115

dB

Rejection Ratio

*Input Voltage Range

q

–14.5

13

–14.5

13

V

(Note 9)

q

0.5

3

0.5

3

V

*Response Time

(Note 7)

150

250

150

250

ns

*Output Saturation Voltage,

0.25

0.40

0.25

0.40

V

q

0.25

0.45

0.25

0.45

V

q

0.70

1.50

0.70

1.50

V

*Output Leakage Current

0.2

10

0.2

10

nA

q

500

500

nA

*Positive Supply Current

3.2

4.0

3.2

4.0

mA

*Negative Supply Current

1.7

2.5

1.7

2.5

mA

*Strobe Current

Minimum to Ensure Output

500

500

µA

(Note 8)

Transistor is Off

Input Capacitance

6

6

pF

LT1011AC/AI/AM

LT1011C/I/M

Note 1: Absolute Maximum Ratings are those values beyond which the

life of a device may be impaired.

Note 2: Inputs may be clamped to supplies with diodes so that

maximum input voltage actually exceeds supply voltage by one diode

drop. See Input Protection in the Applications Information section.

Note 5: These specifications apply for all supply voltages from a single

5V to

±15V, the entire input voltage range, and for both high and low

defines a worst-case error band that includes effects due to common

mode signals, voltage gain and output load.

Note 6: Drift is calculated by dividing the offset voltage difference

measured at min and max temperatures by the temperature difference.

Note 7: Response time is measured with a 100mV step and 5mV

overdrive. The output load is a 500

Ω resistor tied to 5V. Time

measurement is taken when the output crosses 1.4V.

Note 8: Do not short the STROBE pin to ground. It should be current

driven at 3mA to 5mA for the shortest strobe time. Currents as low as

500

µA will strobe the LT1011A if speed is not important. External

leakage on the STROBE pin in excess of 0.2

µA when the strobe is “off”

can cause offset voltage shifts.

Note 9: See graph “Input Offset Voltage vs Common Mode Voltage.”