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SCC2692 Datasheet(PDF) 21 Page - NXP Semiconductors |
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SCC2692 Datasheet(HTML) 21 Page - NXP Semiconductors |
21 / 30 page Philips Semiconductors Product specification SCC2692 Dual asynchronous receiver/transmitter (DUART) 1998 Sep 04 21 NOTES: 1. INTRN or OP3-OP7 when used as interrupt outputs. 2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. VM VOL +0.5V VOL WRN INTERRUPT1 OUTPUT tIR VM VOL +0.5V VOL RDN INTERRUPT1 OUTPUT tIR SD00136 Figure 6. Interrupt Timing X1/CLK CTCLK RxC TxC tCLK tCTC tRx tTx tCLK tCTC tRx tTx +5V 1K X1 X2 C1 = C2 = 24pF FOR CL = 20PF X1 X2 3.6864MHz 3pF 4pF 50 TO 150 K Ω TO INTERNAL CLOCK DRIVERS SCC2698B NOTE: C1 AND C2 SHOULD BE BASED ON MANUFACTURER’S SPECIFICATION. PARASITIC CAPACITANCE SHOULD BE INCLUDED WITH C1 AND C2. R1 IS ONLY REQUIRED IF U1 WILL NOT DRIVE TO X1 INPUT LEVELS TYPICAL CRYSTAL SPECIFICATION FREQUENCY: 2 – 4MHZ LOAD CAPACITANCE (CL): 12 – 32pF TYPE OF OPERATION: PARALLEL RESONANT, FUNDAMENTAL MODE NC R1 U1 SD00137 RESISTOR REQUIRED WHEN U1 IS A TTL DEVICE Figure 7. Clock Timing |
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