Philips Semiconductors

Product specification

SCC2692

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

12

Table 2.

Register Bit Formats (Continued)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SRA

SRB

RECEIVED

BREAK*

FRAMING

ERROR*

PARITY

ERROR*

OVERRUN

ERROR

TxEMT

TxRDY

FFULL

RxRDY

SRB

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits

(7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “reset error status” command. In character mode they are

discarded when the corresponding data character is read from the FIFO. In block error mode, block error conditions must be cleared by using

the error reset command (command 4x) or a receiver reset.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OP7

OP6

OP5

OP4

OP3

OP2

OPCR

0 = OPR[7]

1 = TxRDYB

0 = OPR[6]

1 = TxRDYA

0 = OPR[5]

1 = RxRDY/

FFULLB

0 = OPR[4]

1 = RxRDY/

FFULLA

00 = OPR[3]

01 = C/T OUTPUT

10 = TxCB(1X)

11 = RxCB(1X)

00 = OPR[2]

01 = TxCA(16X)

10 = TxCA(1X)

11 = RxCA(1X)

OPR

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OPR bit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OP pin

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

NOTE:

The level at the OP pin is the inverse of the bit in the OPR register.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ACR

BRG SET

SELECT

COUNTER/TIMER

MODE AND SOURCE

DELTA

IP 3 INT

DELTA

IP 2 INT

DELTA

IP 1 INT

DELTA

IP 0 INT

0 = set 1

1 = set 2

See Table 4

0 = Off

1 = On

0 = Off

1 = On

0 = Off

1 = On

0 = Off

1 = On

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

IPCR

DELTA

IP 3

DELTA

IP 2

DELTA

IP 1

DELTA

IP 0

IP 3

IP 2

IP 1

IP 0

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

0 = Low

1 = High

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ISR

INPUT

PORT

CHANGE

DELTA

BREAK B

RxRDY/

FFULLB

TxRDYB

COUNTER

READY

DELTA

BREAK A

RxRDY/

FFULLA

TxRDYA

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

0 = No

1 = Yes

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

IMR

IN. PORT

CHANGE

INT

DELTA

BREAK B

INT

RxRDY/

FFULLB

INT

TxRDYB

INT

COUNTER

READY

INT

DELTA

BREAK A

INT

RxRDY/

FFULLA

INT

TxRDYA

INT

0 = Off

1 = On

0 = Off

1 = On

0 = Off

1 = On

0 = Off

1 = On

0 = Off

1 = On

0 = Off

1 = On

0 = Off

1 = On

0 = Off

1 = On

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CTUR

C/T[15]

C/T[14]

C/T[13]

C/T[12]

C/T[11]

C/T[10]

C/T[9]

C/T[8]

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CTLR

C/T[7]

C/T[6]

C/T[5]

C/T[4]

C/T[3]

C/T[2]

C/T[1]

C/T[0]