Philips Semiconductors

Product specification

SCC2692

Dual asynchronous receiver/transmitter (DUART)

1998 Sep 04

7

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Max

UNIT

Port input setup time before RDN Low

0

ns

Port input hold time after RDN High

0

ns

400

ns

Interrupt Timing (See Figure 6)

9

INTRN (or OP3-OP7 when used as interrupts) negated from:

9

Read RHR (RxRDY/FFULL interrupt)

300

ns

9

Write THR (TxRDY interrupt)

300

ns

Reset command (break change interrupt)

300

ns

Stop C/T command (counter interrupt)

300

ns

Read IPCR (input port change interrupt)

300

ns

Write IMR (clear of interrupt mask bit)

300

ns

Clock Timing (See Figure 7)

X1/CLK High or Low time

100

ns

X1/CLK frequency

0

3.6864

4

MHz

CTCLK (IP2) High or Low time

100

ns

CTCLK (IP2) frequency

0

4

MHz

RxC High or Low time

220

ns

RxC frequency

(16X)

0

2

MHz

(1X)

0

1

MHz

TxC High or Low time

220

ns

TxC frequency

(16X)

0

1

MHz

(1X)

0

1

MHz

Transmitter Timing (See Figure 8)

TxD output delay from TxC external clock input on IP pin

350

ns

Output delay from TxC low at OP pin to TxD data output

0

150

ns

Receiver Timing (See Figure 9)

RxD data setup time before RxC high at external clock input on IP pin

240

ns

RxD data hold time after RxC high at external clock input on IP pin

200

ns

NOTES:

1. Parameters are valid over specified temperature range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns

maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and

output voltages of 0.8V and 2.0V, as appropriate.

3. Typical values are at +25

°C, typical supply voltages, and typical processing parameters.

5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN

and RDN (also CEN and WRN) are ORed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated

first terminates the cycle.

6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must

7. Guaranteed by characterization of sample units.

8. Minimum frequencies are not tested but are guaranteed by design.

10. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. Crystal frequencies 2 to 4 MHz.