Multilayer ceramic capacitor

B37941K5105K0**

HighCV, X7R 0805 1µF 50 V

Chip

KB VS PE

25.10.2005

Please read Cautions and warnings and

Page 4 of 5

Important notes at the end of this document

Ordering codes and chip thickness

Packing quantity

Size

[inch]

[µF]

Ordering code

Thickness

[mm]

∅ 180-mm reel

[pcs]

∅ 330-mm reel

[pcs]

0805

1

B37941K5105K062*

1.25 ±0.1

3000

12000

* Ordering code example

Standard tolerance:

±10%

Standard packaging:

Blister tape, 180-mm reel

Further information

“Multilayer Ceramic Capacitors” for further information on:

Soldering directions

Taping and packing

Surface mounting instructions

Effects of mechanical stress

Cautions and warnings

Derating: A “state of the art” application design is essential to achieve failures rates at ppb level.

Do not use designs based on 100% of specified rated values.

AC applications may damage MLCC on a much lower level than DC voltage due to power

dissipation losses.

Mechanical stress - Please note EPCOS “General Technical Information”, “Surface mounting

instructions” and information about the effect of mechanical stress.

ESD - EPCOS recommends the use of varistors.

Further processing - care must be taken using moulding processes.

Combined stresses - the total stress (e.g. DC voltage, AC ripple, pulses and temperature) has to

be taken into account to estimate reliability of MLCC.