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MH32S72VJA-6 Datasheet(PDF) 16 Page - Mitsubishi Electric Semiconductor |
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MH32S72VJA-6 Datasheet(HTML) 16 Page - Mitsubishi Electric Semiconductor |
16 / 56 page ![]() MITSUBISHI ELECTRIC 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM MH32S72VJA-6 MITSUBISHI LSIs 8/May. /1999 MIT-DS-0311-0.0 AC TIMING REQUIREMENTS (Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V CK Signal 1.4V 1.4V Any AC timing is referenced to the input signal crossing through 1.4V. LATCH MODE 16 Limits Symbol Parameter Unit tCLK CK cycle time ns tCH CK High pulse width ns tCL CK Low pulse width ns tT Transition time of CK ns tIS Input Setup time(all inputs) ns tIH Input Hold time(all inputs) ns tRC Row Cycle time ns tRCD Row to Column Delay ns tRAS Row Active time ns tRP Row Precharge time ns tWR Write Recovery time ns tRRD Act to Act Deley time ns tRSC Mode Register Set Cycle time ns tREF Refresh Interval time ms CL=3 tSRX Self Refresh Exit time ns Min. Max. 2.5 7.5 2.5 1 10 1.5 0.8 67.5 22.5 45 100K 22.5 15 15 15 64 7.5 CL=4 - ns tRFC Row Refresh Cycle time ns 80 tPDE Power Down Exit time ns 7.5 |
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