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MH32S72BBFA-6 Datasheet(PDF) 17 Page - Mitsubishi Electric Semiconductor |
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MH32S72BBFA-6 Datasheet(HTML) 17 Page - Mitsubishi Electric Semiconductor |
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17 / 56 page  MITSUBISHI ELECTRIC 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM MH32S72BBFA -6 MITSUBISHI LSIs 16/Jun. /1999 MIT-DS-333-0.1 BUFFER MODE SWITCHING CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) LATCH MODE 17 Unit ns ns ns Limits Symbol Parameter tAC Access time from CK CL=3 ns tOH Output Hold time from CK tOLZ Delay time, output low impedance from CK tOHZ Delay time, output high impedance from CK -8 Min. Max. 5.4 2.7 0 2.7 5.4 CL=4 6.0 Limits Symbol Parameter Unit tCLK CK cycle time ns tCH CK High pulse width ns tCL CK Low pilse width ns tT Transition time of CK ns tIS Input Setup time(all inputs) ns tIH Input Hold time(all inputs) ns tRC Row cycle time ns tRCD Row to Column Delay ns tRAS Row Active time ns tRP Row Precharge time ns tWR Write Recovery time ns tRRD Act to Act Deley time ns tPDE Power Down Exit time ns tRSC Mode Register Set Cycle time ns tREF Refresh Interval time ms CL=2 tSRX Self Refresh Exit time ns -6 Min. Max. 2.5 7.5 2.5 1 10 6.5 0 67.5 22.5 45 100000 22.5 15 15 7.5 15 64 7.5 CL=3 10 ns Note:1 The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter. CL=3 CL=4 3.0 |
Similar Part No. - MH32S72BBFA-6 |
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Similar Description - MH32S72BBFA-6 |
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