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MH32S72BBFA-6 Datasheet(PDF) 53 Page - Mitsubishi Electric Semiconductor |
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MH32S72BBFA-6 Datasheet(HTML) 53 Page - Mitsubishi Electric Semiconductor |
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53 / 56 page  MITSUBISHI ELECTRIC 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM MH32S72BBFA -6 MITSUBISHI LSIs 16/Jun. /1999 MIT-DS-333-0.1 Serial Presence Detect Table I Byte Function described SPD enrty data SPD DATA(hex) 0 Defines # bytes written into serial memory at module mfgr 128 80 1 Total # bytes of SPD memory device 256 Bytes 08 2 Fundamental memory type SDRAM 04 3 # Row Addresses on this assembly A0-A11 0C 4 # Column Addresses on this assembly A0-A9 0A 5 # Module Banks on this assembly 2BANK 02 6 Data Width of this assembly... x72 48 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 01 9 SDRAM Cycletime at Max. Supported CAS Latency (CL). 75 Cycle time for CL=3 10 SDRAM Access from Clock 5.4ns 54 tAC for CL=3 11 DIMM Configuration type (Non-parity,Parity,ECC) ECC 02 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM x4 04 14 Error Checking SDRAM data width x4 04 15 Minimum Clock Delay,Back to Back Random Column Addresses 1 01 16 Burst Lengths Supported 1/2/4/8/Full page 8F 17 # Banks on Each SDRAM device 4bank 04 18 CAS# Latency 3 04 19 CS# Latency 0 01 20 Write Latency 0 01 21 SDRAM Module Attributes buffered,registered 1F 22 SDRAM Device Attributes:General Precharge All,Auto precharge Write1/Read Burst 0E 23 SDRAM Cycle time(2nd highest CAS latency) Cycle time for CL=2 00 24 SDRAM Access form Clock(2nd highest CAS latency) tAC for CL=2 25 SDRAM Cycle time(3rd highest CAS latency) N/A 00 N/A 00 26 SDRAM Access form Clock(3rd highest CAS latency) 27 Precharge to Active Minimum 22.5ns 17 28 Row Active to Row Active Min. 15ns 0F 7.5ns N/A 00 N/A 29 RAS to CAS Delay Min 22.5ns 17 30 Active to Precharge Min 45ns 2D 53 |
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Similar Description - MH32S72BBFA-6 |
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