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MH32S72AVJA-6 Datasheet(PDF) 53 Page - Mitsubishi Electric Semiconductor |
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MH32S72AVJA-6 Datasheet(HTML) 53 Page - Mitsubishi Electric Semiconductor |
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53 / 56 page  2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM MH32S72AVJA-6 17.Mar.2000 MIT-DS-0376-0.2 MITSUBISHI LSIs Preliminary Spec. Some contents are subject to change without notice. MITSUBISHI ELECTRIC Serial Presence Detect Table I Byte Function described SPD enrty data SPD DATA(hex) 0 # of Serial PD Bytes Written during Production 128 80 1 Total # of Bytes in SPD device 256 Bytes 08 2 Fundamental memory type SDRAM 04 3 # Row Addresses on this assembly A0-A11 0C 4 # Column Addresses on this assembly A0-A10 0B 5 # Module Banks on this assembly 1BANK 01 6 Data Width of this assembly... x72 48 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 01 9 SDRAM Cycletime at Max. Supported CAS Latency (CL). 75 Cycle time for CL=3 10 SDRAM Access from Clock 5.4ns 54 tAC for CL=3 11 DIMM Configuration type (Non-parity,Parity,ECC) ECC 02 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM x4 04 14 Error Checking SDRAM data width x4 04 15 Minimum Clock Delay,Back to Back Random Column Addresses 1 01 16 Burst Lengths Supported 1/2/4/8/Full page 8F 17 # Banks on Each SDRAM device 4bank 04 18 CAS# Latency 2/3 06 19 CS# Latency 0 01 20 Write Latency 0 01 21 SDRAM Module Attributes buffered,registered with PLL 1F 22 SDRAM Device Attributes:General Precharge All,Auto precharge Write1/Read Burst 0E 23 SDRAM Cycle time(2nd highest CAS latency) Cycle time for CL=2 24 SDRAM Access form Clock(2nd highest CAS latency) 60 tAC for CL=2 25 SDRAM Cycle time(3rd highest CAS latency) N/A 00 N/A 00 26 SDRAM Access form Clock(3rd highest CAS latency) 27 Precharge to Active Minimum 23ns(22.5ns) 17 28 Row Active to Row Active Min. 15ns 0F 7.5ns A0 29 RAS to CAS Delay Min 30 Active to Precharge Min 45ns 2D 53 10ns 6ns 23ns(22.5ns) 17 |
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