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MH32S72AVJA-6 Datasheet(PDF) 41 Page - Mitsubishi Electric Semiconductor |
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MH32S72AVJA-6 Datasheet(HTML) 41 Page - Mitsubishi Electric Semiconductor |
41 / 56 page 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM MH32S72AVJA-6 17.Mar.2000 MIT-DS-0376-0.2 MITSUBISHI LSIs Preliminary Spec. Some contents are subject to change without notice. MITSUBISHI ELECTRIC /CS /RAS /CAS /WE CKE BA0,1 DQ X X X 0 Y 0 Q0 Q0 Q0 ACT#0 READ#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 tRCD Y 1 PRE#1 CLK X X X 1 tRRD Q1 Q1 ACT#1 PRE#0 Q0 DQM read latency=2 1 Y 1 Burst Read is not interrupted by Precharge of the other bank. 0 X X X 1 tRCD tRP READ#1 ACT#1 READ#1 Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case Read Interrupted by Precharge BL=4,CL=3 Buffer mode(REGE="L") REGE A0-9 A10 DQM A11 41 |
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