Philips Semiconductors

Objective specification

TrenchMOS

™ transistor

PSMN009-100W

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Very low on-state resistance

V

• Fast switching

• High thermal cycling performance

I

• Low thermal resistance

R

GENERAL DESCRIPTION

PINNING

SOT429 (TO247)

N-channel

enhancement

mode

PIN

DESCRIPTION

field-effect power transistor in a

plastic envelope using ’trench’

1

gate

technology. The device has very

low

on-state

resistance.

It

is

2

drain

intended for use in dc to dc

converters and general purpose

3

source

switching applications.

tab

drain

The PSMN009-100W is supplied in

the SOT429 (TO247) conventional

leaded package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DSS

Drain-source voltage

T

-

100

V

V

DGR

Drain-gate voltage

T

-

100

V

V

GS

Gate-source voltage

-

± 20

V

I

D

Continuous drain current

T

-

100

1

A

T

-

79

A

I

DM

Pulsed drain current

T

-

300

A

P

D

Total power dissipation

T

-

300

W

T

Operating junction and

- 55

175

˚C

storage temperature

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

E

AS

Non-repetitive avalanche

Unclamped inductive load, I

-

1255

mJ

energy

t

V

I

AS

Non-repetitive avalanche

-

100

A

current

d

g

s

2

3

1

1 Maximum continuous current limited by package.

February 1999

1

Rev 1.000