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MH32D72AKLA-10 Datasheet(PDF) 23 Page - Mitsubishi Electric Semiconductor |
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MH32D72AKLA-10 Datasheet(HTML) 23 Page - Mitsubishi Electric Semiconductor |
23 / 38 page ![]() MITSUBISHI LSIs MITSUBISHI ELECTRIC MH32D72AKLA-10,-75 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0398-1.1 24.Nov.2000 Preliminary Spec. Some contents are subject to change without notice. 23 READ After tRCD from the bank activation, a READ command can be issued. 1st Output data is available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multip le banks. When A10 is high at a READ command, the auto-p recharge(READA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is comp lete. The internal p recharge starts at BL/2 after READA. The next ACT command can be issued after (BL/2+tRP) from the p revious READA. Multi Bank Interleaving READ (BL=8, CL=2(Discrete level)) /CLK Command A0-9,11 A10 BA0,1 DQ ACT Xa Xa 00 READ Y 0 00 READ Y 0 10 ACT Xb Xb 10 PRE 0 00 tRCD Burst Length DQS Qa0 CLK Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb7 Qb8 Module /CAS latency (Discrete CL + 1) |
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