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MH32D72AKLA-10 Datasheet(PDF) 18 Page - Mitsubishi Electric Semiconductor |
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MH32D72AKLA-10 Datasheet(HTML) 18 Page - Mitsubishi Electric Semiconductor |
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18 / 38 page  MITSUBISHI LSIs MITSUBISHI ELECTRIC MH32D72AKLA-10,-75 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0398-1.1 24.Nov.2000 Preliminary Spec. Some contents are subject to change without notice. 18 AC TIMING REQUIREMENTS (Component Level) (Ta=0 ~ 70 , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted) ns 15 10 15 10 CL=2 tCK 0.35 0.35 DQ and DQS data Valid window tDV 19 19 20 ns +0.6 +0.5 DQS-DQ Skew(f or DQS and all DQ signals) tDQSA ns min(tCL,t CH min(tCL, tCH CLK half period tHP tCK 0.55 0.45 0.55 0.45 CLK Low lev el width tCL CLK cyc le time tCK CL=2.5 16 15 14 14 AC Characteristics -10 -75 1.1 0.9 1.1 0.9 0.6 0.4 0.6 0.4 1.2 0.9 1.2 0.9 0.25 0.25 0.6 0.4 0.6 0.4 0 0 15 15 0.2 0.2 0.2 0.2 0.35 0.35 0.35 0.35 1.25 0.75 1.25 0.75 tHP-1.0 tHP-0.75 +0.6 +0.5 +0.8 -0.8 +0.75 -0.75 +0.8 -0.8 +0.75 -0.75 2 1.75 tCK tCK ns ns tCK tCK ns ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns 0.6 0.5 0.6 0.5 15 8 15 7.5 tCK 0.45 0.55 0.45 +0.8 -0.8 +0.75 -0.75 +0.8 -0.8 +0.75 -0.75 Max. Min. Max. Min. Parameter 0.55 Read preamble tRPRE Read postamble tRPST tWPRE Write preamble tWPST Write postamble tWPRES Write preamble setup time Input Hold time (address and control) tIH tIS Input Setup time (address and control) tMRD Mode Register Set command cyc le time tDSH DQS f alling edge hold time f rom CLK tDSS DQS f alling edge to CLK setup time tDQSL DQS input Low lev el width tDQSH DQS input High lev el width tDQSS Write command to f irst DQS latching transition tQH DQ/DQS output hold time f rom DQS tDQSQ DQS-DQ Skew(f or DQS and associated DQ signals) Data-out-low impedance time f rom CLK//CLK tLZ tHZ Data-out-high impedance time f rom CLK//CLK tDIPW DQ and DM input pulse width (f or each input) Input Hold time(DQ,DM) Input Setup time (DQ,DM) tDS tDH tCH CLK High lev el width ns DQ Output Valid data delay time f rom CLK//CLK tDQSCK DQ Output Valid data delay time f rom CLK//CLK ns tAC Notes Unit Sym bol C O |
Similar Part No. - MH32D72AKLA-10 |
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Similar Description - MH32D72AKLA-10 |
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