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MH32D72AKLA-10 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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MH32D72AKLA-10 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
1 / 38 page ![]() MITSUBISHI LSIs MITSUBISHI ELECTRIC MH32D72AKLA-10,-75 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0398-1.1 24.Nov.2000 Preliminary Spec. Some contents are subject to change without notice. 1 DESCRIPTION APPLICATION Main memoryunit for PC, PC server FEATURES Type name 133MHz MH32D72AKLA-10 MH32D72AKLA-75 - Utilizes industry standard 32M X 4 DDR Synchronous DRAMs in TSOP package , industry standard Registered Buffer in TSSOP package , and industry standard PLL in TSSOP package. - Vdd=Vddq=2.5v ±0.2V - Double data rate architecture; two data transf ers per clock cyc le - Bidirectional, data strobe (DQS) is transmitted/receiv ed with data - Diff erential clock inputs (CLK and /CLK) - data ref erenced to both edges of DQS - /CAS latency - 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Auto precharge / All bank precharge controlled by A10 - 4096 ref resh cyc les /64ms - Auto ref resh and Self ref resh - Row address A0-11 / Column address A0-9,11 - SSTL_2 Interf ace - Module 1bank Conf igration - Burst Ty pe - sequential/interleav e(programmable) - Commands entered on each positiv e CLK edge Max. Frequency 100MHz 1pin 52pin 92pin 93pin 144pin 145pin 184pin The MH32D72AKLA is 33554432 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module. This consists of 18 industry standard 32M x 4 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz. This socket-ty pe memory m odule is suitable f or main memory in computer systems and easy to interchange or add modules. CLK Access Time [component level] 53pin + 0.75ns + 0.8ns |
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