MH32D72AKLA-10 datasheet(34/38 Pages) MITSUBISHI

Part #	MH32D72AKLA-10

Description	2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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34 / 38 page

MITSUBISHI LSIs

MITSUBISHI ELECTRIC

MH32D72AKLA-10,-75

2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MIT-DS-0398-1.1

24.Nov.2000

Preliminary Spec.

Some contents are subject to change without notice.

34

[Power DOWN]

The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh

mode. A command at cy cle is ignored. From CKE=H to normal function, DLL recovery time is NOT

required in the condition of the stable CLK op eration during the power down mode.

/CLK

CLK

Power Down by CKE

Command

PRE

CKE

Command

ACT

CKE

Standby Power Down

Active Power Down

NOP

Valid

NOP

Valid

tXPNR/

tXPRD

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