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MH32D72AKLA-10 Datasheet(PDF) 25 Page - Mitsubishi Electric Semiconductor |
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MH32D72AKLA-10 Datasheet(HTML) 25 Page - Mitsubishi Electric Semiconductor |
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25 / 38 page  MITSUBISHI LSIs MITSUBISHI ELECTRIC MH32D72AKLA-10,-75 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0398-1.1 24.Nov.2000 Preliminary Spec. Some contents are subject to change without notice. 25 WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the WRITE command with data strobe input, following (BL-1) data are written into RAM , when the Burst Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multip le banks. From the last data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE command, the auto-p recharge(WRITEA) is p erformed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal p recharge is comp lete. The next ACT command can be issued after tDAL from the last input data cycle. WRITE with Auto-Precharge (BL=8) Command A0-9,11 A10 BA0,1 DQ ACT Xa 00 WRITE 1 00 ACT Xb 00 tRC D Da0 DQS /CLK CLK Da1 Da2 Da3 Da4 Da5 Da6 Da7 tDAL Xa Y Xb Multi Bank Interleaving WRITE (BL=8) Command A0-9,11 A10 BA0,1 DQ ACT Xa 00 WRITE 00 WRITE 0 0 10 ACT Xb 10 0 10 tRC D tRC D PRE Xa 0 00 PRE DQS /CLK CLK Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7 Xa Ya Yb Xb Module input and output timing. Module input and output timing. |
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