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PCF8583P Datasheet(PDF) 16 Page - NXP Semiconductors |
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PCF8583P Datasheet(HTML) 16 Page - NXP Semiconductors |
16 / 28 page ![]() 1997 Jul 15 16 Philips Semiconductors Product specification Clock/calendar with 240 × 8-bit RAM PCF8583 9I2C-BUS PROTOCOL 9.1 Addressing Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.16. Bit A0 corresponds to hardware address pin A0. Connecting this pin to VDD or VSS allows the device to have one of two different addresses. 9.2 Clock/calendar READ/WRITE cycles The I2C-bus configuration for the different PCF8583 READ and WRITE cycles is shown in Figs 17, 18 and 19. Fig.16 Slave address. handbook, halfpage MRB016 101 00 0 A0 R/W group 1 group 2 Fig.17 Master transmits to slave receiver (WRITE) mode. handbook, full pagewidth S 0A SLAVE ADDRESS WORD ADDRESS A A DATA P acknowledgement from slave acknowledgement from slave acknowledgement from slave R/W auto increment memory word address MBD822 n bytes |
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