 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PCF8583P Datasheet(PDF) 12 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCF8583P Datasheet(HTML) 12 Page - NXP Semiconductors |
|
|
12 / 28 page  1997 Jul 15 12 Philips Semiconductors Product specification Clock/calendar with 240 × 8-bit RAM PCF8583 Fig.10 Alarm control register, event-counter mode. handbook, full pagewidth memory location 08 reset state: 0000 0000 timer function : 000 no timer 001 units 010 100 011 10 000 100 1 000 000 101 not allowed 110 not allowed 111 test mode, all counters in parallel timer interrupt enable : 0 timer flag, no interrupt 1 timer flag, interrupt clock alarm function : 00 no event alarm 01 event alarm 10 not allowed 11 not allowed timer alarm enable : 0 no timer alarm 1 timer alarm alarm interrupt enable : 0 alarm flag, no interrupt 1 alarm flag, interrupt 7 654 321 0 MSB LSB MRB007 In the clock mode, if the alarm enable is not activated (alarm enable bit of control/status register is logic 0), the interrupt output toggles at 1 Hz with a 50% duty cycle (may be used for calibration). This is the default power-on state of the device. The OFF voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 V. A logic diagram of the interrupt output is shown in Fig.11. 7.10 Oscillator and divider A 32.768 kHz quartz crystal has to be connected to OSCI (pin 1) and OSCO (pin 2). A trimmer capacitor between OSCI and VDD is used for tuning the oscillator (see quartz frequency adjustment). A 100 Hz clock signal is derived from the quartz oscillator for the clock counters. In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high impedance state. This allows the user to feed the 50 Hz reference frequency or an external high speed event signal into the input OSCI. 7.11 Initialization When power-up occurs the I2C-bus interface, the control/status register and all clock counters are reset. The device starts time-keeping in the 32.768 kHz clock mode with the 24 h format on the first of January at 0.00.00: 00. A 1 Hz square wave with 50% duty cycle appears at the interrupt output pin (starts HIGH). It is recommended to set the stop counting flag of the control/status register before loading the actual time into the counters. Loading of illegal states may lead to a temporary clock malfunction. |
Similar Part No. - PCF8583P |
|
Similar Description - PCF8583P |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
