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CDCL1810RGZRG4 Datasheet(PDF) 13 Page - Texas Instruments |
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CDCL1810RGZRG4 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 25 page  www.ti.com Byte 3: Byte 4: Byte 5: Byte 6: CDCL1810 SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 Bit Power Up Bit Name Description/Function Type Condition Reference To 7 RES Reserved R/W 0 6 RES Reserved R/W 0 5 RES Reserved R/W 0 4 PH0[4] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 2, Table 3 3 PH0[3] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 2, Table 3 2 PH0[2] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 2, Table 3 1 PH0[1] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 2, Table 3 0 PH0[0] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 2, Table 3 Power Up Bit Bit Name Description/Function Type Condition Reference To 7 RES Reserved R/W 0 6 RES Reserved R/W 0 5 ENP0 Post-divider P0 enable. If 0, output YP[4:0] and YN[4:0] are disabled R/W 1 4 RES Reserved R/W 1 3 SELP0[3] Divide ratio select for post-divider P0 R/W 0 Table 1 2 SELP0[2] Divide ratio select for post-divider P0 R/W 0 Table 1 1 SELP0[1] Divide ratio select for post-divider P0 R/W 0 Table 1 0 SELP0[0] Divide ratio select for post-divider P0 R/W 0 Table 1 Power Up Bit Bit Name Description/Function Type Condition Reference To 7 EN Chip enable; if 0 chip is in Iddq mode R/W 1 6 RES Reserved R 1 5 ENDRV9 YP[9], YN[9] enable; if 0 output is disabled R/W 1 4 ENDRV8 YP[8], YN[8] enable; if 0 output is disabled R/W 1 3 ENDRV7 YP[7], YN[7] enable; if 0 output is disabled R/W 1 2 ENDRV6 YP[6], YN[6] enable; if 0 output is disabled R/W 1 1 ENDRV5 YP[5], YN[5] enable; if 0 output is disabled R/W 1 0 ENDRV4 YP[4], YN[4] enable; if 0 output is disabled R/W 1 Power Up Bit Bit Name Description/Function Type Condition Reference To 7 ENDRV3 YP[3], YN[3] enable; if 0 output is disabled R/W 1 6 ENDRV2 YP[2], YN[2] enable; if 0 output is disabled R/W 1 5 ENDRV1 YP[1], YN[1] enable; if 0 output is disabled R/W 1 4 ENDRV0 YP[0], YN[0] enable; if 0 output is disabled R/W 1 3 RES Reserved R/W 0 2 RES Reserved R/W 0 1 RES Reserved R/W 0 0 RES Reserved R/W 0 13 Submit Documentation Feedback |
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