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AM29LV800DB120ED Datasheet(PDF) 19 Page - SPANSION |
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AM29LV800DB120ED Datasheet(HTML) 19 Page - SPANSION |
19 / 46 page Am29LV800D_00_A7 December 4, 2006 Am29LV800D 17 D A TA SH EET Note: See Table 5 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any con- trols or timings during these operations. Table 5 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embed- ded Erase algorithm are ignored. Note that a hard- ware reset dur ing the chip er ase oper ation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the de- vice has returned to reading array data, to ensure data integrity. The system can determine the status of the erase op- eration by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these sta- tus bits. When the Embedded Erase algorithm is com- plete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase opera- tion. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 5 shows the address and data requirements for the sector erase command se- quence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase al- gorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between addi- tional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the de- vice to reading array data. The system must rewrite the command sequence and any additional sector ad- dresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command se- quence. START Write Program Command Sequence Data Poll from System Verify Data? No Yes Last Address? No Yes Programming Completed Increment Address Embedded Program algorithm in progress |
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