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ICL7665SACPAZ Datasheet(PDF) 3 Page - Intersil Corporation |
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ICL7665SACPAZ Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 14 page ![]() 3 FN3182.8 April 5, 2006 Absolute Maximum Ratings Thermal Information Supply Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V Output Voltages OUT1 and OUT2 . . . . . . . . . . . . . . . . . -0.3V to 18V (with respect to GND) (Note 2) Output Voltages HYST1 and HYST2 . . . . . . . . . . . . . . -0.3V to +18V (with respect to V+) (Note 2) Input Voltages SET1 and SET2 . . . . . (GND -0.3V) to (V+ V- +0.3V) (Note 2) Maximum Sink Output OUT1 and OUT2 . . . . . . . . . . . . . . . . . 25mA Maximum Source Output Current HYST1 and HYST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA Operating Conditions Temperature Range ICL7665SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 °C to 70°C ICL7665SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 °C to 85°C Thermal Resistance (Typical, Note 1) θJA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . . 150°C Maximum Junction Temperature (CERDIP). . . . . . . . . . . . . . . 175°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages greater than (V+ +0.3V) or less than (GND - 0.3V) may cause destructive device latchup. For these reasons, it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICL7665S be turned on first. If this is not possible, current into inputs and/or outputs must be limited to ±0.5mA and voltages must not exceed those defined above. Electrical Specifications The specifications below are applicable to both the ICL7665S and ICL7665SA. V+ = 5V, TA = 25°C, Test Circuit Figure 7. Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage V+ ICL7665S TA = 25°C1.6 - 16 V 0°C ≤ TA ≤ 70°C1.8 - 16 V -25°C ≤ TA ≤ 85°C1.8 - 16 V ICL7665SA 0°C ≤ TA ≤ 70°C1.8 - 16 V -25°C ≤ TA ≤ 85°C1.8 - 16 V Supply Current I+ GND ≤ VSET1, VSET2 ≤ V+, All Outputs Open Circuit 0°C ≤ TA ≤ 70°C V+ = 2V - 2.5 10 µA V+ = 9V - 2.6 10 µA V+ = 15V - 2.9 10 µA -40°C ≤ TA ≤ 85°C V+ = 2V - 2.5 10 µA V+ = 9V - 2.6 10 µA V+ = 15V - 2.9 10 µA Input Trip Voltage VSET1 ICL7665S 1.20 1.30 1.40 V VSET2 1.20 1.30 1.40 V VSET1 ICL7665SA 1.275 1.30 1.325 V VSET2 1.275 1.30 1.325 V Temperature Coefficient of VSET ∆VSET ∆T ICL7665S - 200 - ppm ICL7665SA - 100 - ppm Supply Voltage Sensitivity of VSET1, VSET2 ∆VSET ∆VS ROUT1, ROUT2, RHYST1, R2HYST2 = 1MΩ, 2V ≤ V+ ≤ 10V -0.03- %/V ICL7665S |
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