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USB97CFDC2-01 Datasheet(PDF) 17 Page - SMSC Corporation |
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USB97CFDC2-01 Datasheet(HTML) 17 Page - SMSC Corporation |
17 / 24 page ![]() SMSC DS – USB97CFDC2-01 Page 17 Rev. 02-27-07 DATASHEET 9 AC PARAMETERS t2 t1 t2 CLOCKI FIGURE 1 - INPUT CLOCK TIMING Table 2 – Input Clock Timing Parameters NAME DESCRIPTION MIN TYP MAX UNITS t1 Clock Cycle Time for 14.318MHz 69.84 ns t2 Clock High Time/Low Time for 24MHz 41.9/ 27.9 27.9/ 41.9 ns tr, tf Clock Rise Time/Fall Time (not shown) 5 ns FA [0:19 ] FD [7:0 nFR D nFW R t1 t5 t3 t4 t2 FIGURE 2 – FLASH READ TIMING Table 3 – Flash Read Timing NAME PARAMETER MIN TYP MAX UNITS t1 FA[14:0] Address setup time to nFRD asserted 40 ns t2 nFRD pulse width 110 ns t3 FD[7:0] Data setup time to nFRD de-asserted 30 ns t4 FD[7:0] Data hold time from nFRD de-asserted 0 ns t5 FA[14:0] Address hold time from nFRD de-asserted 35 ns |
Similar Part No. - USB97CFDC2-01 |
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Similar Description - USB97CFDC2-01 |
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