January 1995

5

Philips Semiconductors

Product specification

Phase-locked loop

HEF4046B

MSI

Phase comparator 2 is an edge-controlled digital memory

network. It consists of four flip-flops, control gating and a

3-state output circuit comprising p and n-type drivers

having a common output node. When the p-type or n-type

not of importance.

If the signal input frequency is higher than the comparator

input frequency, the p-type output driver is maintained ON

most of the time, and both the n and p-type drivers are

OFF (3-state) the remainder of the time. If the signal input

frequency is lower than the comparator input frequency,

the n-type output driver is maintained ON most of the time,

and both the n and p-type drivers are OFF the remainder

of the time. If the signal input and comparator input

frequencies are equal, but the signal input lags the

comparator input in phase, the n-type output driver is

maintained ON for a time corresponding to the phase

difference. If the comparator input lags the signal input in

phase, the p-type output driver is maintained ON for a time

corresponding to the phase difference. Subsequently, the

voltage at the capacitor of the low-pass filter connected to

this phase comparator is adjusted until the signal and

comparator inputs are equal in both phase and frequency.

At this stable point, both p and n-type drivers remain OFF

and thus the phase comparator output becomes an open

circuit and keeps the voltage at the capacitor of the

low-pass filter constant.

Moreover, the signal at the phase comparator pulse output

a locked condition. Thus, for phase comparator 2 no phase

difference exists between the signal and comparator

inputs over the full VCO frequency range. Moreover, the

power dissipation due to the low-pass filter is reduced

when this type of phase comparator is used because both

p and n-type output drivers are OFF for most of the signal

input cycle. It should be noted that the PLL lock range for

this type of phase comparator is equal to the capture

range, independent of the low-pass filter. With no signal

present at the signal input, the VCO is adjusted to its

lowest frequency for phase comparator 2 . Figure 5 shows

typical waveforms for a PLL employing this type of phase

comparator in locked condition.

Fig.5 Typical waveforms for phase-locked loop employing phase comparator 2 in locked condition.