6

A second division is performed using the remainder from the

first division (in Y) as the more significant 8N-bits of the divi-

dend and the less significant half of the original dividend

loaded into the Z register. The divisor in X remains unaltered

and is, by definition, larger than the remainder from the first

division which is in Y. The resulting value in Z becomes the

less significant 8N-bits of the final quotient and the value in Y

is, as usual, the remainder.

Extending this technique to more steps allows division of any

size number by an 8N-bit divisor.

Note that division by zero is never permitted and must be

tested for and handled in software.

The following example illustrates the use of this algorithm.

Example:

Assume three MDU's capable of a by 24-bit division. The

problem is to divide 00F273, 491C06H by 0003B4H.

The Z register can simply be reset using bit 2 of the control

word and another divide can be done in order to further

divide the remainder.

3. Multiply Operation

For a multiply operation the two numbers to be multiplied are

loaded in the X and Z registers. The result is in the Y and Z

register with Y being the more significant half and Z the less

significant half. The X register will be unchanged after the

operation is completed.

The original contents of the Y register are added to the

product of X and Z. Bit 3 of the control word will reset

register Y to 0 if desired.

Functional Description of

CDP1855 Terminals

CE - Chip Enable (Input):

A high on this pin enables the CDP1855 MDU to respond to

the select lines. All cascaded MDU's must be enabled

together. CE also controls the three-state C.O./O.F., output

of the most significant MDU.

Clear (Input):

The CDP1855 MDU(s) must be cleared upon power-on with

a low-on this pin. The clear signal resets the sequence

counters, the shift pulse generator, and bits 0 and 1 of the

control register.

CTL - Control (Input):

This is an input pin. All CTL pins must be wired together and

used to indicate whether the registers are to be operated on

or only shifted.

C.O./O.F. - Carry Out/Over Flow (Output):

This is a three-state output pin. It is the CDP1855 Carry Out

signal and is connected to Cl (CARRY-IN) of the next more

significant CDP1855 MDU, except for on the most significant

MDU. On that MDU it is an overflow indicator and is enabled

when chip enables is true. A low on this pin indicates that an

overflow has occurred. The overflow signal is latched each

time the control register is loaded, but is only meaningful

after a divide command.

These are three-state bi-directional pins for data transfer

between the Y registers of cascaded CDP1855 MDU's. The

significant MDU and to the CTL pins of all MDU's. Also the

most significant MDU.

These are three-state bi-directional pins for data transfers

most significant MDU.

Shift - Shift Clock:

This is a three-state bi-directional pin. It is an output on the

most significant MDU. And an input on all other MDU's. It

provides the MDU system timing pulses. All SHIFT pins must

be connected together for cascaded operation. A maximum

of the 8N +1 shifts are required for an operation where "N"

equals the number of MDU devices that are cascaded.

CLK - Clock (Input):

This pin should be grounded on all but the most significant

MDU. There is an optional reduction of clock frequency

available on this pin if so desired, controlled by bit 7 of the

control byte.

STB - Strobe (Input):

When RD/WE is low, data is latched from bus lines on the

falling edge of this signal. It may be asynchronous to the

clock. Strobe also increments the selected register's

sequence counter during reads and writes. TPB would be

used in CDP1800 systems.

Step 1:

000000

,

00F273

/

0003B4

=

000041

R=0001BF

Y

Z(MS)

X

Z1

Y1

Step 2: 0001BF

,

491C06

/

0003B4

=

78C936

R=00000E

Y1

Z(LS)

X

Z2

Y2

Result:

000041

,

78C936

R=00000E

Z1

Z2

Y2

CDP1855, CDP1855C