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HEF4017BP Datasheet(PDF) 5 Page - NXP Semiconductors |
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HEF4017BP Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 8 page January 1995 5 Philips Semiconductors Product specification 5-stage Johnson counter HEF4017B MSI AC CHARACTERISTICS VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C L HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL VDD V SYMBOL MIN. TYP. MAX. Hold times 5 90 45 ns CP0 →CP1 10 thold 40 20 ns 15 20 10 ns 580 40 ns CP1 → CP0 10 thold 40 20 ns 15 30 10 ns Minimum clock pulse width: 5 tWCPL = tWCPH 80 40 ns CP0 = LOW; 10 40 20 ns see also waveforms CP1 = HIGH 15 30 15 ns Figs 4 and 5 Minimum MR 5 50 25 ns pulse width; HIGH 10 tWMRH 30 15 ns 15 20 10 ns Recovery time 5 60 30 ns for MR 10 tRMR 30 15 ns 15 20 10 ns Maximum clock 5 6 12 MHz pulse frequency 10 fmax 12 24 MHz 15 15 30 MHz VDD V TYPICAL FORMULA FOR P ( µW) Dynamic power 5 500 fi +∑ (foCL) × VDD2 where dissipation per 10 2200 fi +∑ (foCL) × VDD2 fi = input freq. (MHz) package (P) 15 6000 fi +∑ (foCL) × VDD2 fo = output freq. (MHz) CL = load cap. (pF) ∑ (f oCL) = sum of outputs VDD = supply voltage (V) VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA |
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